In an A/D conversion system configured by using a delta-sigma modulator, an input signal, which is a voltage signal, is filtered by a loop filter and an output of the loop filter is quantized by a quantizer. In a case that a capacitance value of a capacitor used in the loop filter has an error (variation), a gain of the loop filter including the capacitor becomes erroneous and hence an A/D conversion result becomes erroneous. In a case that an input signal is A/D converted by an A/D conversion system of a single loop type, which has no cascade configuration, the above-described error is negligible. However, it needs many operation cycles and a longer period to output the A/D conversion result.
When input signals outputted from plural sensors are A/D converted sequentially by switching over the input signals, the input signals need be switched over by dividing A/D conversion periods for each input signal. For this reason, that is, for switching over the input signals at high speeds, an A/D conversion system of the cascade type is used. In comparison to the A/D conversion system of the single loop type, which has no cascade configuration, the A/D conversion system of the cascade type has a problem that influence of the A/D conversion error becomes relatively large.
For example, JP 4862943 (patent document) discloses a delta-sigma A/D conversion system of a hybrid incremental type, which is one example of the cascade type. This A/D conversion system cancels the conversion error at the end of a predetermined A/D conversion period.
However, the configuration of the patent document has the following problem. According to the patent document, first-order delta-sigma modulation is performed by sampling an input signal Vin by charging a capacitor with the input signal and connecting repetitively conversion signals, which are used as reference signals in a D/A converting operation, to the capacitor, in accordance with an output signal of a quantizer, which performs a quantizing operation. The output of the quantizer is integrated to generate higher bits (more significant bits) of an A/D conversion result. The A/D conversion system, which uses the first-order delta-sigma modulation, is susceptible to error caused by limitation of a gain of an operational amplifier. An amplifier is required to have a high gain to be less susceptible to the influence of error. Such an amplifier consumes more power and needs a large circuit area. In addition, for improving the resolution in the A/D conversion of a first-order delta-sigma modulator, more operation cycles are required relative to a higher-order delta-sigma modulator. It is thus difficult to increase the number of conversion bits.
In the patent document, the delta-sigma A/D conversion system is configured as the hybrid incremental type. That is, an output of an integrator is A/D converted after a delta-sigma conversion to generate lower bits of an A/D conversion result, and the lower bits thus generated are added to the higher bits generated by the delta-sigma modulation. According to the hybrid incremental type delta-sigma A/D converter, which is one example of the cascade type, the error in the output of the integrator used for the delta-sigma modulation influences the accuracy of A/D conversion. Therefore, an operation for cancelling the error of the integrator is performed so that the accuracy of A/D conversion is improved. However, this error cancellation needs additional operation cycles and increases the period required for A/D conversion.
According to the patent document, the conversion signals are supplied to all of sampling capacitors, to which the input signal is inputted. As a result, a full scale of the A/D conversion (a range of the input signal that the A/D converter can convert the input signal) and a range of the conversion signals become equal. Generally, the range of the input signal hardly exceeds a range of a power supply voltage (voltage between power source and ground). For example, in a case that an amplifier circuit is provided at a pre-stage, the range of the input signal is limited by the output signal range of the amplifier circuit (normally between ½ and ¾ of the power supply voltage).
In a case that the range of the input signal is narrower than the range of the power supply voltage, the ranges of the conversion signals are set to be narrower than the range of the power supply voltage so that the full scale of the A/D conversion is matched to the range of the input signal. In a case that the conversion signals is set to the power supply voltage, only a part of the full scale of the A/D conversion is used for the input signal. In a case that the conversion signals are set to be in narrow ranges without being set to the power supply voltage and the ground, regulators need be provided exclusively for stabilizing the conversion signals. In a case that the conversion signal is set to the power supply voltage, only a part of the full scale of the A/D converter is used as the input signal range. As a result, the resolution is decreased or the number of conversion cycles is increased to compensate for a decrease of the resolution.
As a method of adjusting the full scale of the A/D conversion for eliminating the above-referred problems it is proposed to set the conversion signal to the power supply voltage and input the conversion signal to only a part of the sampling capacitors so that the conversion signal is decreased equivalently. In this case, however, removal of error from the output of the loop filter by the error canceling operation is incomplete. That is, in the delta-sigma A/D converter of the cascade type, the removal of error from the output of the loop filter remains insufficient.
Further, since the output signal range of an amplifier, which is a structural component of the A/D conversion system, is limited (normally about ½ to ¾ of the power supply voltage), it is necessary to limit the output signal of the amplifier not to exceed the limit in the course of the A/D conversion. To maintain the output signal of the amplifier not to exceed the limit, both of the range of the input signal and the range of the conversion signals may be narrowed. This narrowed ranges result that the full scale of the A/D converter is also narrowed. If the full scale of the A/D conversion system is narrowed, noises become more influential. To counter this problem, a circuit area for a capacitor and an amplifier need be increased and power consumption will be increased.
A range of a signal, which is outputted from the amplifier in the course of the A/D conversion, may be narrowed by increasing a capacitance value of an integrating capacitor of a delta-sigma modulator to be greater than a sum of capacitance values of sampling capacitors. By setting the capacitance value of the sampling capacitor as disclosed in the patent document, a gain of a modulator is set to ½ thereby to narrow the output signal range of the amplifier. However, when the error cancellation is performed, the gain becomes doubled as a reciprocal of ½. Further, since outputs of two first-order delta-sigma modulators are added, the output signal range of the amplifier becomes wider. If an amplifier having a wider output signal range is used to solve the above-referred problems, a circuit area and power consumption need be increased.